Special Seminar - Prof. Jason Cong, Distinguished Professor, UCLA Computer Science
Department
Friday, Oct. 14, 2022
1:00 PM - 2:00 PM,
Science and Engineering Complex
Room: SEC 2.118
Attend In-person or on
Zoom<https://harvard.zoom.us/j/93115310667?pwd=UWpKNVQ0OFlvSllDS1cxYzFzMk92Zz09>
Democratizing IC Designs and Customized Computing
As we enter the era of customized computing, where customized domain-specific accelerators
(DSAs) are used extensively for performance and energy efficiency. Ideally, we would like
to enable every programmer should offload the compute-intensive portion of his/her program
to one or a set of DSAs, either pre-implemented in ASICs or synthesized on demand on
programmable fabrics, such as FPGAs. But integrated circuit (IC) designs remain a black
art to many. High-level synthesis (HLS) made an important progress in simplify IC
designs, but it still requires the programmer to provide various pragmas, such as loop
unroll, pipelining, and tiling, to define the microarchitecture of the accelerator, which
is a challenging task to most software programmer. In this talk, we present our latest
research on automated accelerator synthesis and customized computing on FPGAs, ranging
from microarchitecture guided optimization, such as automated generation of highly
optimized systolic arrays and stencil computation engines, to more general
source-to-source transformation based on graph-based neural networks and meta learning,
and finally to latency-insensitive system-level integration.
Speaker Bio:
JASON CONG is the Volgenau Chair for Engineering Excellence Professor at the UCLA Computer
Science Department (and a former department chair), with joint appointment from the
Electrical and Computer Engineering Department. He is the director of Center for
Domain-Specific Computing (CDSC) and the director of VLSI Architecture, Synthesis, and
Technology (VAST) Laboratory. Dr. Cong’s research interests include novel architectures
and compilation for customizable computing, synthesis of VLSI circuits and systems, and
highly scalable algorithms. He has over 500 publications in these areas, including 16
best paper awards, and three papers in the FPGA and Reconfigurable Computing Hall of Fame.
He and his former students co-founded AutoESL, which developed the most widely used
high-level synthesis tool for FPGAs (renamed to Vivado HLS after Xilinx’s acquisition).
He was elected to an IEEE Fellow in 2000, ACM Fellow in 2008, the National Academy of
Engineering in 2017, and the National Academy of Inventors in 2020. He is the recipient
of the 2022 IEEE Robert Noyce Medal for fundamental contributions to electronic design
automation and FPGA design methods.
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