[Aspuru-Guzik Group List] EE Seminar on Friday, November 30th - James Clarke

[hseas-logo] Harvard John A. Paulson School of Engineering and Applied Sciences Electrical Engineering Seminar Series James Clarke Intel Corporation “Towards a Large Scale Quantum Computer using Advanced Fabrication Technologies” Friday, November 30, 2018 3:00 – 4:00 p.m. Maxwell Dworkin G125 Light refreshments Today’s quantum processors are limited to 10’s of entangled quantum bits. If you believe the hype, a commercially relevant system is just around the corner that can outperform our largest supercomputers. The reality, however, is that we are at mile 1 of a marathon. There are many unanswered fundamental questions. At Intel, our approach is to rely on the continued evolution of Moore’s Law to build qubit arrays with a high degree of process control. Here, we present progress toward the realization of 300mm Si-MOS based spin qubit devices in a production environment. This includes (i) isotopically purified28Si epi substrates with a compelling LT Hall mobility of ~ 10,000 cm2/Vs, (ii) design of a custom qubit layout, (iii) integration of fin-based spin qubit devices using immersion lithography, moving from classical transistor structures to full spin qubits, and (iv) the realization of quantum dots in a nested gate design novel to a 300mm process line. In addition, this talk will focus on two bottlenecks to moving beyond today’s few-qubit devices. The first bottleneck is in the interconnect design of the quantum circuit. Today’s qubits have personalities. Individual control of each qubit is required. A small quantum processor today has multiple RF and DC wires per qubit. This is a brute force approach to wiring and will not scale to the millions of qubits needed for large applications. The second bottleneck relates to the speed of information turns in quantum development. Fabrication of spin qubits in a silicon substrate bares similarity to conventional transistors from advanced CMOS technologies. One of the above 300mm wafers has over 10,000 individual quantum test structures. Naturally, R&D should be accelerated by the potential volume of statistical data. While automated electrical testing of a CMOS transistor wafer can be completed in less than an hour at room temperature, data collection at cryogenic temperatures is currently limited to a small number of devices with a turnaround of hours to days. Rhetorically speaking, “How can we deliver an exponentially fast compute technology with slow and serial characterization of quantum chips?” Speaker: Jim Clarke is the director of the Quantum Hardware research group within Intel’s Components Research Organization. Jim launched Intel’s Quantum Computing effort in 2015, as well as a research partnership with QuTech (TU Delft and TNO). His group’s primary focus is to use Intel’s process expertise to develop scalable qubit arrays. Prior to his current role, Jim managed a group focused on interconnect research at advanced technology nodes as well as evaluating new materials and paradigms for interconnect performance. He has co-authored more than 70 papers and has several patents. Prior to joining Intel in 2001, Jim completed a B.S. in chemistry at Indiana University, a Ph.D. in physical chemistry at Harvard University and a post-doctoral fellowship in physical organic chemistry at ETH, Zürich. Host: Marko Loncar